DAC architectures are well known in the art. Fully segmented or thermometer coded architectures are well known and widely used in DAC's as the main DAC of a segmented converter or as the whole DAC itself.
It will be understood that the minimum number of elements selected for a segmented DAC will depend on the application to which the DAC is applied. In certain applications, a fully segmented DAC has 2N unitary elements, where N is the resolution of the converter, whereas in other applications, it may have 2N−1 elements depending on whether the output for input code 0 is zero or one LSB (least significant bit). Each element, if selected, contributes the output equivalent to a least significant bit. The elements are typically selected from circuit components such as current sources, resistors, capacitors or the like as will be well known to those skilled in the art. DAC's are sometimes categorised as charge-scaling, voltage-scaling or current scaling DAC's. An example of a segmented DAC 100 is shown in FIG. 1. Here, it will be seen a digital input word 105 is fed to a decoder 110. Based on the decoding effected for that choice of input word, one or more of the 2N available elements 115 are selected to provide the equivalent analog output.
Examples of known architectures include those of U.S. Pat. No. 6,452,527, which describes how current sources of in a conventional segmented architecture DAC may be switched in a certain order so that the non-linearities in the DAC caused by gradients are improved.
Another known technique is described in G. A. M. Van der Plas et. al. “A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC”, IEEE Journal of Solid State Circuits, Vol. 34, No. 12, pp. 1708–1718, December 1999. Here, a segmented N-bit DAC is described having 16×2N sub-segments with each one of the individual sub-segments having a weighting of 1/16 of an LSB. The architecture is arranged so as to spread each segment (made up of 16 sub-segments) in the layout to cancel errors due to gradients in the process.
C. Wegener and MP Kennedy describe the use of an arbitrary segment configuration for calibration of an N-bit DAC architecture having 2N segments (“Linear model based error identification and calibration for data converters”, Europe Conference and Exhibition in Design, Automation and Test 2003, pp 630–635, 2003). They describe how each of the segments may be measured and then recombined on decoding. However, the accuracy improvement after calibration is not very high.
There therefore still exists a need to provide an improved DAC, which is specifically adapted to provide for high accuracy applications.